公开(公告)号：US11495280B2

公开(公告)日：2022-11-08

申请号：US17399349

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongseok Seo ,  Kwanghyun Kim ,  Chikook Kim ,  Seungwoo Ryu ,  Doohee Hwang

IPC: G11C11/40 ,  G11C11/4072 ,  H01L25/065

Abstract: A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.