公开(公告)号：US20250118662A1

公开(公告)日：2025-04-10

申请号：US18735507

申请日：2024-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun Kwon ,  Sunoo Kim ,  Jonghwa Park ,  Yongseung Bang ,  Jaeheon Lee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer disposed on a first surface of the semiconductor substrate, a through via passing through both the semiconductor substrate and the first insulating layer, a protective barrier wall pattern disposed within the first insulating layer and on a sidewall of the through via, a first wiring structure disposed within the first insulating layer and including a first via portion and a first wiring portion, and a second insulating layer disposed on an upper surface of the first insulating layer and at least partially covering an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.

公开(公告)号：US20200335348A1

公开(公告)日：2020-10-22

申请号：US16708504

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Kwon

IPC: H01L21/308 ,  H01L21/768 ,  H01L23/00

Abstract: Methods of manufacturing an integrated circuit device are provided. A method of manufacturing an integrated circuit device includes sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening and a second mask layer having a second opening as an etch mask, respectively. The method includes forming a first wiring recess through the wiring insulating layer and a second wiring recess having a depth that is less than that of the first wiring recess by removing a portion of the wiring insulation layer by using a portion of the hard mask layer as an etching mask. Moreover, the method includes forming a wiring structure that is in the first wiring recess and the second wiring recess.

公开(公告)号：US10796920B1

公开(公告)日：2020-10-06

申请号：US16708504

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Kwon

IPC: H01L21/308 ,  H01L23/00 ,  H01L21/768

Abstract: Methods of manufacturing an integrated circuit device are provided. A method of manufacturing an integrated circuit device includes sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening and a second mask layer having a second opening as an etch mask, respectively. The method includes forming a first wiring recess through the wiring insulating layer and a second wiring recess having a depth that is less than that of the first wiring recess by removing a portion of the wiring insulation layer by using a portion of the hard mask layer as an etching mask. Moreover, the method includes forming a wiring structure that is in the first wiring recess and the second wiring recess.