公开(公告)号：US20180342283A1

公开(公告)日：2018-11-29

申请号：US15869803

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-jun LEE ,  Seung-jun SHIN ,  Hoon SIN ,  Ik-joon CHOI ,  Ju-seong HWANG

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.