公开(公告)号：US20220413725A1

公开(公告)日：2022-12-29

申请号：US17903540

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-kyu CHOI ,  Ki-seok OH ,  Seung-jun SHIN ,  Hye-ran KIM

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/4074

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

公开(公告)号：US20190138245A1

公开(公告)日：2019-05-09

申请号：US16010814

申请日：2018-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-jun SHIN ,  Hyong-ryol HWANG

IPC: G06F3/06 ,  G11C8/18 ,  G06F12/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1024 ,  G06F2212/1044 ,  G11C7/1018 ,  G11C8/18

Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.

公开(公告)号：US20180342283A1

公开(公告)日：2018-11-29

申请号：US15869803

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-jun LEE ,  Seung-jun SHIN ,  Hoon SIN ,  Ik-joon CHOI ,  Ju-seong HWANG

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.

公开(公告)号：US20180121124A1

公开(公告)日：2018-05-03

申请号：US15797525

申请日：2017-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-kyu CHOI ,  Ki-seok OH ,  Seung-jun SHIN ,  Hye-ran KIM

IPC: G06F3/06 ,  G11C11/406

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.