公开(公告)号：US20240172457A1

公开(公告)日：2024-05-23

申请号：US18497027

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji Noh ,  Jongho Woo ,  Jooheon Kang ,  Kyunghoon Kim ,  Myunghun Woo

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A vertical memory device may include a cell stacked structure on a substrate, wherein the cell stacked structure includes an insulation layer pattern and a gate pattern are alternately and repeatedly stacked, and wherein the cell stacked structure extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked region is disposed in the second region and has a step portion having a step shape; an etch stop structure on an upper surface of each of gate patterns of the step portion of the cell stacked structure, wherein the etch stop structure includes a transition metal oxide; an insulating interlayer covering the cell stacked structure; and a contact plug passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns.

公开(公告)号：US20250120076A1

公开(公告)日：2025-04-10

申请号：US18653571

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonkang Choi ,  Jongho Woo ,  Sangwoo Han

IPC: H10B41/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device and an electronic system including the device are presented. The device includes a substrate, a stacked structure with a plurality of gate electrodes on the substrate and spaced apart from each other, a first channel structure, and a second channel structure. The first channel structure includes a first channel layer extending through the stacked structure and a first ferroelectric layer positioned between the first channel layer and the stacked structure. The second channel structure includes a second channel layer with a first portion extending through the selection gate electrode, a second portion extending through the insulating pattern to contact an upper surface of the first channel layer, and a third portion protruding from a lower surface of the second portion and contacting an outer surface of the first channel layer.