公开(公告)号：US20160204041A1

公开(公告)日：2016-07-14

申请号：US14988991

申请日：2016-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkook KIM ,  Wooseok KO ,  Yusin YANG ,  Sangkil LEE ,  Chungsam JUN

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method of inspecting a semiconductor device includes providing a substrate, on which a mold layer with a plurality of mold openings is provided, milling the mold layer in a direction inclined at a predetermined angle with respect to a direction normal to a top surface of the substrate, such that an inclined cutting surface exposing milled mold openings is formed, the milled mold openings including first milling openings along a first column extending in a first direction and having different heights, obtaining image data of the cutting surface, the image data including first contour images of the first milling openings, and obtaining a first process parameter, which represents an extent of bending of the mold openings according to a distance from a top surface of the substrate, using positions of center points of the first contour images.

Abstract translation: 一种检查半导体器件的方法包括提供一个衬底，在其上提供具有多个模具开口的模具层，在相对于垂直于该顶部表面的方向倾斜预定角度的方向上铣削模具层 基板，使得形成露出铣削模具开口的倾斜切割表面，所述铣削模具开口包括沿着第一方向延伸并具有不同高度的第一列的第一铣削开口，获得切割表面的图像数据，所述图像数据包括第一 并且使用第一轮廓图像的中心点的位置获得第一加工参数，该第一加工参数代表与基材顶表面距离的距离的模具开口的弯曲程度。

公开(公告)号：US20230021071A1

公开(公告)日：2023-01-19

申请号：US17949305

申请日：2022-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/1159 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20210280230A1

公开(公告)日：2021-09-09

申请号：US17330828

申请日：2021-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20200381393A1

公开(公告)日：2020-12-03

申请号：US16689769

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkil LEE ,  So-young KIM ,  Soo-woong AHN

IPC: H01L25/065 ,  H01L23/538

Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.

公开(公告)号：US20230290754A1

公开(公告)日：2023-09-14

申请号：US18318975

申请日：2023-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkil LEE ,  So-young Kim ,  Soo-woong Ahn

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5383 ,  H01L29/42392

Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.