公开(公告)号：US20210328582A1

公开(公告)日：2021-10-21

申请号：US17215838

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon KANG ,  Woo Kyu KIM ,  Tae Jun YOO ,  Dal Hee LEE

IPC: H03K3/037 ,  H03K3/012 ,  H03K19/20

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.

公开(公告)号：US20220345118A1

公开(公告)日：2022-10-27

申请号：US17861939

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon KANG ,  Woo Kyu KIM ,  Tae Jun YOO ,  Dal Hee LEE

IPC: H03K3/037 ,  H03K19/20 ,  H03K3/012 ,  H03K3/3562

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.