公开(公告)号：US11387817B2

公开(公告)日：2022-07-12

申请号：US17215838

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon Kang ,  Woo Kyu Kim ,  Tae Jun Yoo ,  Dal Hee Lee

IPC: H03K3/037 ,  H03K19/20 ,  H03K3/012 ,  H03K3/3562

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.

公开(公告)号：US11996846B2

公开(公告)日：2024-05-28

申请号：US17861939

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon Kang ,  Woo Kyu Kim ,  Tae Jun Yoo ,  Dal Hee Lee

IPC: H03K3/037 ,  H03K3/012 ,  H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/3562 ,  H03K19/20

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.