公开(公告)号：US11651800B2

公开(公告)日：2023-05-16

申请号：US17354613

申请日：2021-06-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Feng Lu ,  Jongyeon Kim ,  Ohwon Kwon

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1087

Abstract: A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

公开(公告)号：US11620050B2

公开(公告)日：2023-04-04

申请号：US17359945

申请日：2021-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： A Harihara Sravan ,  Yan Li ,  Feng Lu

IPC: G06F3/06

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

公开(公告)号：US20220406342A1

公开(公告)日：2022-12-22

申请号：US17354613

申请日：2021-06-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Feng Lu ,  Jongyeon Kim ,  Ohwon Kwon

IPC: G11C7/06 ,  G11C7/10

Abstract: A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

公开(公告)号：US20220129163A1

公开(公告)日：2022-04-28

申请号：US17359945

申请日：2021-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： A Harihara Sravan ,  Yan Li ,  Feng Lu

IPC: G06F3/06

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.