公开(公告)号：US12112827B2

公开(公告)日：2024-10-08

申请号：US17852664

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hwan Kim ,  Jun Young Park ,  Jin Do Byun ,  Kwang Seob Shin ,  Eun Seok Shin ,  Hyun-Yoon Cho ,  Young Don Choi ,  Jung Hwan Choi

IPC: G11C7/10 ,  H03K19/00

CPC classification number: G11C7/1048 ,  G11C2207/2254 ,  H03K19/0005

Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

公开(公告)号：US12094563B2

公开(公告)日：2024-09-17

申请号：US17805940

申请日：2022-06-08

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangling Ji

IPC: H03K19/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  H03K19/0185

CPC classification number: G11C7/1006 ,  G11C7/1048 ,  G11C11/4093 ,  G11C11/4096 ,  H03K19/0185

Abstract: The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

公开(公告)号：US20240304271A1

公开(公告)日：2024-09-12

申请号：US18668593

申请日：2024-05-20

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh

IPC: G11C29/42 ,  G11C7/10 ,  G11C8/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1048 ,  G11C7/1063 ,  G11C8/18 ,  G11C29/1201

Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

公开(公告)号：US12062411B2

公开(公告)日：2024-08-13

申请号：US17732272

申请日：2022-04-28

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Minki Jeong ,  Wanyeong Jung

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/12 ,  G11C11/54

CPC classification number: G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/54

Abstract: A semiconductor device includes a cell block and a data block. The cell block includes an operation circuit having a first capacitor and a second capacitor and an input circuit configured to couple the first capacitor and the second capacitor to a bit line according to differential voltages provided via word lines and corresponding to a first data. The data block includes a capacitor array having a variable capacitance corresponding to a value of a second data; and a coupling switch configured to couple the bit line and the data block. The cell block and the data block may be used to perform a Multiply and Accumulate (MAC) operation.

公开(公告)号：US20240241647A1

公开(公告)日：2024-07-18

申请号：US18215183

申请日：2023-06-28

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G11C7/1048 ,  G11C2207/2254

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

公开(公告)号：US20240194232A1

公开(公告)日：2024-06-13

申请号：US18587961

申请日：2024-02-27

Applicant: SK hynix Inc.

Inventor： Jinhyung Lee ,  Myeong Jae PARK ,  Su Hyun OH ,  Chang Kwon LEE

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1072 ,  G11C5/06 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1087

Abstract: A semiconductor device comprising: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

公开(公告)号：US11990195B2

公开(公告)日：2024-05-21

申请号：US17935057

申请日：2022-09-23

Applicant: Lodestar Licensing Group LLC

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C7/10 ,  G11C11/406 ,  G11C29/14 ,  G11C29/44

CPC classification number: G11C29/12015 ,  G11C7/1048 ,  G11C11/40615 ,  G11C29/14 ,  G11C29/44

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

公开(公告)号：US11984192B2

公开(公告)日：2024-05-14

申请号：US17841432

申请日：2022-06-15

Applicant: Western Digital Technologies, Inc.

Inventor： Mordekhay Zehavi ,  Mahmud Asfur ,  Yossef Tamir ,  Yuri Ryabinin

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22 ,  G11C29/52

CPC classification number: G11C7/1048 ,  G11C5/14 ,  G11C7/1039 ,  G11C7/22 ,  G11C29/52

Abstract: Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

公开(公告)号：US11978528B2

公开(公告)日：2024-05-07

申请号：US17649326

申请日：2022-01-28

Applicant: Infineon Technologies LLC

Inventor： Shivananda Shetty ,  Yoram Betser ,  Pawan Singh ,  Stefano Amato ,  Alexander Kushnarenko

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

公开(公告)号：US20240127871A1

公开(公告)日：2024-04-18

申请号：US18235848

申请日：2023-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donggun An ,  Jaehyeok Baek ,  Sungyong Cho ,  Moonchul Choi

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.