公开(公告)号：US20210280559A1

公开(公告)日：2021-09-09

申请号：US16808128

申请日：2020-03-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Kirubakaran Periyannan ,  Jayavel Pachamuthu ,  Narendhiran CR ,  Jay Dholakia ,  Everett Lyons, IV ,  Hoang Huynh ,  Dat Dinh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/525

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

公开(公告)号：US20180188956A1

公开(公告)日：2018-07-05

申请号：US15398495

申请日：2017-01-04

Applicant: SanDisk Technologies LLC

Inventor： Narendhiran CR ,  Satya Kesav Gundabathula ,  Muralitharan Jayaraman ,  Chittoor Devarajan Sunilkumar ,  Satrajit Chakraborty

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0688

Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.