公开(公告)号：US20210280559A1

公开(公告)日：2021-09-09

申请号：US16808128

申请日：2020-03-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Kirubakaran Periyannan ,  Jayavel Pachamuthu ,  Narendhiran CR ,  Jay Dholakia ,  Everett Lyons, IV ,  Hoang Huynh ,  Dat Dinh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/525

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

公开(公告)号：US20190187553A1

公开(公告)日：2019-06-20

申请号：US15845456

申请日：2017-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel J. Linnen ,  Jianhua Zhu ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G03F1/50

CPC classification number: G03F1/50

Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

公开(公告)号：US20190171506A1

公开(公告)日：2019-06-06

申请号：US15834050

申请日：2017-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sukhminder Singh Lobana ,  Kirubakaran Periyannan

IPC: G06F11/07 ,  G11C29/00

Abstract: A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the usable portion of the incomplete memory structure are identified. During operation of the memory system, the memory system receives logical addresses for memory operations to be performed on the partial memory die and determines physical addresses that corresponding to the logical addresses. The memory system performs an out of bounds response for a physical address that is on the partial memory die but outside of the one or more rectangular zones. The memory system performs memory operations for physical addresses that are inside the one or more rectangular zones.

公开(公告)号：US20180350445A1

公开(公告)日：2018-12-06

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10

CPC classification number: G11C29/1201 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

公开(公告)号：US20190129861A1

公开(公告)日：2019-05-02

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/657 ,  G11C5/02 ,  G11C7/1039 ,  G11C8/06 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2207/107

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US20210373085A1

公开(公告)日：2021-12-02

申请号：US16883718

申请日：2020-05-26

Applicant: SanDisk Technologies LLC

Inventor： Dat Tran ,  Loc Tu ,  Kirubakaran Periyannan ,  Nyi Nyi Thein

IPC: G01R31/52 ,  G01R31/64 ,  G01R31/26

Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

公开(公告)号：US10991447B2

公开(公告)日：2021-04-27

申请号：US16451421

申请日：2019-06-25

Applicant: SanDisk Technologies LLC

Inventor： Daniel Linnen ,  Avinash Rajagiri ,  Dongxiang Liao ,  Kirubakaran Periyannan

IPC: G11C29/56 ,  G06F11/16 ,  G11C16/32 ,  G11C5/14

Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

公开(公告)号：US20190130978A1

公开(公告)日：2019-05-02

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

公开(公告)号：US10141064B1

公开(公告)日：2018-11-27

申请号：US15585680

申请日：2017-05-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kirubakaran Periyannan ,  Daniel Joseph Linnen

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/08 ,  G11C16/14

Abstract: Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.

公开(公告)号：US11372056B2

公开(公告)日：2022-06-28

申请号：US16883718

申请日：2020-05-26

Applicant: SanDisk Technologies LLC

Inventor： Dat Tran ,  Loc Tu ,  Kirubakaran Periyannan ,  Nyi Nyi Thein

IPC: G01R31/52 ,  G01R31/26 ,  G01R31/64

Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.