公开(公告)号：US10854629B2

公开(公告)日：2020-12-01

申请号：US16368007

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Jixin Yu ,  Fabo Yu ,  Xin Yuan Li ,  Yanli Zhang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11519

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.

公开(公告)号：US20200312865A1

公开(公告)日：2020-10-01

申请号：US16368007

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Jixin Yu ,  Fabo Yu ,  Xin Yuan Li ,  Yanli Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.

公开(公告)号：US10658381B1

公开(公告)日：2020-05-19

申请号：US16367455

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Fumiaki Toyama ,  Masaaki Higashitani ,  Tong Zhang ,  Chun Ge ,  Xin Yuan Li ,  Johann Alsmeier

IPC: H01L27/11565 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573

Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.