公开(公告)号：US20190172841A1

公开(公告)日：2019-06-06

申请号：US16269360

申请日：2019-02-06

Applicant: SOCIONEXT INC.

Inventor： Keisuke KISHISHITA

IPC: H01L27/118 ,  H01L27/02

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. In a standard cell including nanowire FETs connected in series through an intermediate node used only for mutual connection, the nanowire FETs include first, second, and third pads, Na nanowires extending in an X direction between the first and second pads to connect the first and second pads together, and Nb nanowires extending in the X direction between the second and third pads to connect the second and third pads together.

公开(公告)号：US20190074297A1

公开(公告)日：2019-03-07

申请号：US16182342

申请日：2018-11-06

Applicant: SOCIONEXT INC.

Inventor： Keisuke KISHISHITA ,  Hiroyuki SHIMBO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L23/482 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Provided is a layout configuration that helps facilitate manufacturing a semiconductor integrated circuit device including a nanowire FET. A nanowire FET in a standard cell includes Na (where Na is an integer of 2 or more) nanowires extending in an X direction, and a nanowire FET in a standard cell includes Nb (where Nb is an integer of 1 or more and less than Na) nanowires extending in the X direction. At least one of both ends, in the Y direction, of a pad of the nanowire FET is aligned in the X direction with an associated one of both ends, in the Y direction, of a pad of the nanowire FET.

公开(公告)号：US20180269154A1

公开(公告)日：2018-09-20

申请号：US15987275

申请日：2018-05-23

Applicant: SOCIONEXT INC.

Inventor： Keisuke KISHISHITA

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/11807 ,  H01L2027/11881

Abstract: The present disclosure can reduce power consumption of a semiconductor integrated circuit device using a power interruption technique, without increasing the area of the device and the number of man hours required for design. A power supply strap is formed in a layer above a power supply line which supplies power to standard cells. A switch cell is provided for the power supply line, the switch cell being capable of switching between electrical connection and disconnection between the power supply line and the power supply strap. A sub-power supply strap is connected to at least two power supply lines including the power supply line provided with the switch cell.