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公开(公告)号：US11621259B2
公开(公告)日：2023-04-04
申请号：US17233177
申请日：2021-04-16
申请人： SOCIONEXT INC.
发明人： Toshihiro Nakamura , Taro Fukunaga
IPC分类号： H01L27/02 , H01L23/528 , H01L23/00
摘要： A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.
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公开(公告)号：US20230046171A1
公开(公告)日：2023-02-16
申请号：US17864966
申请日：2022-07-14
申请人： Socionext Inc.
摘要： A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry. The control circuitry controls the at least one offset-correction circuit to: control an amount by which the offset-correction signal is adjusted; and/or in a bypass operation, connect the input terminal of the at least one controllable offset-correction component to a bypass-operation reference voltage supply; and/or in a maintenance operation, control the charging-operation voltage supply and/or the bypass-operation voltage supply to control leakage of the charge stored on the holding capacitor.
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公开(公告)号：US20230042275A1
公开(公告)日：2023-02-09
申请号：US17966396
申请日：2022-10-14
申请人： Socionext Inc.
发明人： Yukihiro SASAGAWA
摘要： A network quantization method is a network quantization method of quantizing a neural network, and includes a database construction step of constructing a statistical information database on tensors that are handled by neural network, a parameter generation step of generating quantized parameter sets by quantizing values included in each tensor in accordance with the statistical information database and the neural network, and a network construction step of constructing a quantized network by quantizing the neural network with use of the quantized parameter sets. The parameter generation step includes a quantization-type determination step of determining a quantization type for each of a plurality of layers that make up the neural network.
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公开(公告)号：US11574751B2
公开(公告)日：2023-02-07
申请号：US16721193
申请日：2019-12-19
申请人： SOCIONEXT INC.
摘要： A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X
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公开(公告)号：US20230036535A1
公开(公告)日：2023-02-02
申请号：US17850202
申请日：2022-06-27
申请人： Socionext Inc.
发明人： Saul DARZY , Ozcan TUNCTURK
IPC分类号： H03K17/687 , H03M1/12 , H03M1/66
摘要： A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.
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公开(公告)号：US20230034555A1
公开(公告)日：2023-02-02
申请号：US17859658
申请日：2022-07-07
申请人： Socionext Inc.
摘要： Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.
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公开(公告)号：US11563985B2
公开(公告)日：2023-01-24
申请号：US16257317
申请日：2019-01-25
申请人： Socionext Inc.
IPC分类号： G06F9/38 , H04N19/86 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/436 , H04N19/523
摘要： A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.
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公开(公告)号：US11550962B2
公开(公告)日：2023-01-10
申请号：US16867911
申请日：2020-05-06
申请人： SOCIONEXT INC.
发明人： Seiji Goto , Jun Kamada , Taiji Tamiya
IPC分类号： G06F12/16 , G06F12/14 , G06F11/00 , G06F21/74 , G06F21/52 , G06F21/55 , G06F21/57 , G06F21/64 , G06F21/71 , G06F21/72 , G06F21/70 , G06F21/53 , G06F12/1027 , G06F13/24
摘要： The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.
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公开(公告)号：US20220392999A1
公开(公告)日：2022-12-08
申请号：US17889106
申请日：2022-08-16
申请人： Socionext Inc.
发明人： Junji IWAHORI
IPC分类号： H01L29/06 , H01L27/02 , H01L27/092 , H01L23/528 , G11C11/412 , H01L27/11 , H01L27/118
摘要： A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.
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公开(公告)号：US20220367442A1
公开(公告)日：2022-11-17
申请号：US17877534
申请日：2022-07-29
申请人： Socionext Inc.
发明人： Taro FUKUNAGA , Masahisa IIDA , Toshihiro NAKAMURA
IPC分类号： H01L27/02
摘要： In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.
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