公开(公告)号：US10056917B2

公开(公告)日：2018-08-21

申请号：US15397921

申请日：2017-01-04

Applicant: SOLiD, Inc.

Inventor： Donghoon Hong ,  Hosik Jang ,  Youngin Kim

IPC: H03M7/30 ,  G06F7/485 ,  G06F7/556 ,  G06F7/48

CPC classification number: H03M7/30 ,  G06F7/4824 ,  G06F7/483 ,  G06F7/485 ,  G06F7/556 ,  H03M7/24

Abstract: A data compression device includes an analog to digital converter (ADC) configured to convert an analog signal into a digital signal including in-phase and quadrature components; and a compressor configured to generate a 28-bit fixed-point digital signal in which bits of the in-phase and quadrature components are alternately arranged, generate an exponent bit string by comparing n most significant bits of a data bit string excluding two sign bits in the 28-bit fixed-point digital signal with preset mapping data, wherein the exponent bit string includes 4 bits, generate a mantissa bit string composed of 14 bits corresponding to up to 14th bit from a bit next to the n most significant bits of the data bit string, and generate a 20-bit floating point digital signal by combining the two sign bits, the exponent bit string, and the mantissa bit string, wherein n is a natural number equal to or greater than 2 and equal to or less than 12.