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公开(公告)号：US20240176619A1
公开(公告)日：2024-05-30
申请号：US18435993
申请日：2024-02-07
申请人： Intel Corporation
IPC分类号： G06F9/30 , G06F7/483 , G06F7/50 , G06F7/523 , G06F7/556 , G06F30/34 , G06F30/343 , G06F30/38 , G06N20/00 , H03K19/177 , H03K19/17748 , H03M7/24
CPC分类号： G06F9/30101 , G06F7/50 , G06F7/523 , G06F7/556 , G06F9/30105 , G06F30/34 , G06F30/343 , G06F30/38 , G06N20/00 , H03K19/177 , H03K19/17748 , H03M7/24 , G06F7/483
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
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公开(公告)号：US20240152322A1
公开(公告)日：2024-05-09
申请号：US18407854
申请日：2024-01-09
申请人： SK hynix Inc.
发明人： Seong Ju LEE
摘要： An accumulator includes an exponent data latch circuit configured to output first exponent data of input data and second exponent data of latch data in synchronization with a first clock signal, a mantissa data latch circuit configured to output first mantissa data of the input data and second mantissa data of the latch data in synchronization with an edge of a second clock signal delayed by a delay time period later than an edge of the first clock signal, an exponent processing circuit configured to perform an exponent processing operation that generates first shift data and second shift data based on the first exponent data and the second exponent data transmitted from the exponent data latch circuit, and a mantissa processing circuit configured to shift the first mantissa data and the second mantissa data transmitted from the mantissa data latch circuit by the first shift data and the second shift data, respectively.
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公开(公告)号：US20230359438A1
公开(公告)日：2023-11-09
申请号：US18029375
申请日：2020-10-16
发明人： Dai IKARASHI
摘要： Provided is a secure computation technique for efficiently uniforming exponent parts of floating points. A secret exponent part uniforming system which, from a share ([[→a]]P, [[→ρ]]Q) of a floating point vector (→a= (a0,..., am-1), →ρ=(ρ0, ..., ρm-1)), calculates a share ([[~b]]P, [[→ρmax]]Q) of a floating point vector with uniformed exponent parts (→b= (b0,..., bm-1), →ρmax=(ρmax, ..., ρmax) (ρmax=max{ρ0, ..., ρm-1}), 2ρ_iai≒2ρ_maxbi is satisfied), comprises a mantissa part calculation means for calculating a share [[→b]]P by calculating a share [[bi]]P (bi=2-ρ_dif,iai) of the number bi from the i-th element of the share [[→a]]P and the i-th element of a share >Q converted by replicated secret sharing from a share
[[→ρdif]]Q=[[→ρ]]Q-[[→ρmax]]Q.-
公开(公告)号：US20230185533A1
公开(公告)日：2023-06-15
申请号：US18165802
申请日：2023-02-07
发明人： Ren LI , Prajakt KULKARNI , Suren MOHAN , Aaron Douglass LAMB
摘要： Certain aspects of the present disclosure provide a method for processing input data by a set of configurable nonlinear activation function circuits, including generating an exponent output by processing input data using one or more first configurable nonlinear activation function circuits configured to perform an exponential function, summing the exponent output of the one or more first configurable nonlinear activation function circuits, and generating an approximated log softmax output by processing the summed exponent output using a second configurable nonlinear activation function circuit configured to perform a natural logarithm function.
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公开(公告)号：US20230176819A1
公开(公告)日：2023-06-08
申请号：US17542016
申请日：2021-12-03
申请人： Xilinx, Inc.
发明人： Ming Ruan
CPC分类号： G06F7/556 , G06F7/5443 , G06F7/57
摘要： Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk−1), generates output z-terms 0 through (Nk/2−1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term 2i and the input r-term. The multiply-and-accumulate circuitry in decimation stages k for k≤(V−1) provides the output r-term and one or more output z-terms from decimation stage k as the input r-term and one or more input z-terms to the respective multiply-and-accumulate circuitry of decimation stage k+1. A recursive stage inputs from decimation stage V, the output r-term as a recursive r-term and the output z-terms as a-terms, and generates a polynomial output value z by a recursive evaluation of the recursive r-term, the a-terms, and a modulus, p.
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公开(公告)号：US10056917B2
公开(公告)日：2018-08-21
申请号：US15397921
申请日：2017-01-04
申请人： SOLiD, Inc.
发明人： Donghoon Hong , Hosik Jang , Youngin Kim
摘要： A data compression device includes an analog to digital converter (ADC) configured to convert an analog signal into a digital signal including in-phase and quadrature components; and a compressor configured to generate a 28-bit fixed-point digital signal in which bits of the in-phase and quadrature components are alternately arranged, generate an exponent bit string by comparing n most significant bits of a data bit string excluding two sign bits in the 28-bit fixed-point digital signal with preset mapping data, wherein the exponent bit string includes 4 bits, generate a mantissa bit string composed of 14 bits corresponding to up to 14th bit from a bit next to the n most significant bits of the data bit string, and generate a 20-bit floating point digital signal by combining the two sign bits, the exponent bit string, and the mantissa bit string, wherein n is a natural number equal to or greater than 2 and equal to or less than 12.
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公开(公告)号：US09859909B1
公开(公告)日：2018-01-02
申请号：US15446702
申请日：2017-03-01
发明人： Joshua Cowan
CPC分类号： H03M1/1235 , G06F7/556 , H03K7/08 , H03M1/58 , H05B33/0845
摘要： A method and system of an analog to digital conversion having an exponential result are provided. An analog input signal is received by the ramp ADC. The analog input signal is converted into an N-bit digital signal having a linear relationship with the analog input signal. An internal gated clock signal is generated based on the received first clock signal. The gated clock signal is used as an input to an M-bit register. An output of the M-bit register is multiplied by a predetermined factor. The product of the multiplication is provided as an input to the M-bit register. The output of the M-bit register provides an M-bit output having an exponential relationship with the analog input signal.
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公开(公告)号：US09477442B2
公开(公告)日：2016-10-25
申请号：US14479392
申请日：2014-09-08
申请人： FUJITSU LIMITED
发明人： Mikio Hondo
CPC分类号： G06F7/556 , G06F7/483 , G06F2207/483 , G06F2207/556
摘要： A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.
摘要翻译： 处理器包括：指数生成单元，其基于接收到的输入数据的第一部分生成由浮点数格式表示的系数的指数部分，将指数函数分解为串联运算时获得的系数，并且系数 用于系列操作; 存储单元，其存储所述系数的尾数部分; 常数生成单元，其从所述存储单元读取与所述输入数据的第二部分相对应的恒定数据; 以及选择单元，当要执行的指令是用于计算指数函数的系数的系数计算指令时，从常数生成单元中选择并输出常数数据。
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9.发明授权Digital signal processor having instruction set with an xK function using reduced look-up table 有权数字信号处理器具有使用减少的查找表的具有xK功能的指令集公开(公告)号：US09207910B2
公开(公告)日：2015-12-08
申请号：US12362874
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
摘要翻译： 提供了一种数字信号处理器，其具有使用减少的查找表的具有xK功能的指令集。 所公开的数字信号处理器通过在硬件中计算Log（x）来评估输入值x的xK函数; 将Log（x）值乘以K; 以及通过在硬件中对乘法步骤的结果应用指数函数来确定xK函数。 Log（x）和指数函数的计算中的一个或多个使用至少一个查找表，其具有比输入值x中的位数少的位数较少的条目。
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公开(公告)号：US09064299B2
公开(公告)日：2015-06-23
申请号：US13948789
申请日：2013-07-23
申请人： Karl P. Sims
发明人： Karl P. Sims
摘要： The technology described in this document relates to filters and functions that are based on exponential decay functions. In one aspect, the technology is embodied in a method that includes using a computing device to compute a first function as a combination of (i) an exponential decay function, a decay factor for which is chosen based on a Gaussian function, and (ii) at least a second function that is obtained by one or more convolution operations on the decay function. The first function provides an approximation of at least a portion of the Gaussian function.
摘要翻译： 本文中描述的技术涉及基于指数衰减函数的滤波器和函数。 在一个方面，该技术体现在一种方法中，该方法包括使用计算设备来计算第一函数作为（i）指数衰减函数，基于高斯函数选择的衰减因子和（ii） ）至少一个通过对衰减函数的一个或多个卷积运算而获得的函数。 第一个函数提供高斯函数的至少一部分的近似。
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