公开(公告)号：US20150309897A1

公开(公告)日：2015-10-29

申请号：US14442071

申请日：2013-08-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Chaoxuan TIAN ,  Huafang SUN ,  Longxing SHI

IPC: G06F11/20

CPC classification number: G06F11/2035 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/3024 ,  G06F11/3062 ,  G06F11/3093 ,  G06F2201/805 ,  G06F2201/85 ,  Y02D10/126 ,  Y02D10/172

Abstract: Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

Abstract translation: 公开了面向CPU装配线的错误恢复电路，包括：片上监控电路（1），误差信号统计模块（2），电压频率控制模块（3），错误恢复控制模块（4） 原位错误恢复模块（5）和上层错误恢复模块（6），其中片上监控电路（1）中的每一个在前一个N- 1级具有N级组装线结构的CPU内核的组装线，以便监视关于操作电路的每个时钟周期的时间序列信息，其中N是大于或等于3的正整数，以及 小于20.本发明提供了在具有N级装配线的CPU内核上的在线时间序列监视，以搜索电路的最低可能工作电压，并且减小为电路保留的工作电压的余量 在设计阶段，从而得到信誉 显着降低电路的功耗并提高电路的能量效率。