公开(公告)号：US11335387B2

公开(公告)日：2022-05-17

申请号：US17042921

申请日：2019-10-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Tao Wang

IPC: G11C7/06 ,  G11C7/10 ,  G06N3/063 ,  G11C7/12 ,  G11C8/08 ,  H03K3/356 ,  H03K19/21

Abstract: An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.