公开(公告)号：US12237839B2

公开(公告)日：2025-02-25

申请号：US18448946

申请日：2023-08-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Siman Li ,  Yoonjoo Eom

IPC: H03L7/087 ,  H03K19/21 ,  H03L7/183

Abstract: A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.

公开(公告)号：US12222390B2

公开(公告)日：2025-02-11

申请号：US18457537

申请日：2023-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Samuel Paul Visalli

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  H03K19/21

Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

公开(公告)号：US12212321B1

公开(公告)日：2025-01-28

申请号：US18340827

申请日：2023-06-23

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Ikenna Odinaka ,  Rajeev Kumar Dokania ,  Rafael Rios ,  Sasikanth Manipatruni

IPC: H03K3/027 ,  H01L49/02 ,  H03K19/185 ,  H03K19/21 ,  H03K19/23 ,  G11C7/10

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

公开(公告)号：US12166480B2

公开(公告)日：2024-12-10

申请号：US17346034

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Chinmay Joshi ,  Dinesh Somasekhar

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/21

Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

公开(公告)号：US20240311082A1

公开(公告)日：2024-09-19

申请号：US18194894

申请日：2023-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saurabh Shankar ZOND ,  Debojyoti Banerjee ,  Abhishek Ghosh ,  Raghavendra Shirodkar ,  Rakesh Dimri ,  Yashaswini H G

IPC: G06F7/501 ,  H03K19/20 ,  H03K19/21

CPC classification number: G06F7/501 ,  H03K19/20 ,  H03K19/215

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.

公开(公告)号：US12088305B2

公开(公告)日：2024-09-10

申请号：US17442143

申请日：2020-03-17

Applicant: Eaton Intelligent Power Limited

Inventor： Horea-Stefan Culca

IPC: H03K5/153 ,  G01R19/165 ,  G01R19/175 ,  H03K5/1536 ,  H03K19/21

CPC classification number: H03K5/1536 ,  G01R19/16547 ,  G01R19/175 ,  H03K19/21

Abstract: A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.

公开(公告)号：US12068751B2

公开(公告)日：2024-08-20

申请号：US17852657

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Tyler J. Gomm

IPC: G11C11/4076 ,  G11C7/22 ,  H03K5/1534 ,  H03K5/156 ,  H03K19/21

CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K5/1534 ,  H03K19/21

Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

公开(公告)号：US12068746B2

公开(公告)日：2024-08-20

申请号：US17773945

申请日：2020-11-02

Applicant: Nanyang Technological University

Inventor： Chu Keong Gerard Joseph Lim ,  Chandrasekhar Murapaka ,  Wen Siang Lew

IPC: G11C11/16 ,  G11C11/18 ,  H03K19/18 ,  H03K19/21 ,  H10N52/00

CPC classification number: H03K19/18 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H03K19/21 ,  H10N52/00

Abstract: A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.

公开(公告)号：US12066487B2

公开(公告)日：2024-08-20

申请号：US17766965

申请日：2020-10-19

Applicant: Robert Bosch GmbH

Inventor： Andreas Schubert

IPC: G01R31/317 ,  H03H7/06 ,  H03K19/21 ,  H03K3/037

CPC classification number: G01R31/31727 ,  H03H7/06 ,  H03K19/21 ,  H03K3/037

Abstract: A method for simple measurement of phase shift between a first clock signal and a second clock signal is described, each clock signal having a period T0. The method includes: feeding the first clock signal into a first input of a mixer; feeding the second clock signal into a second input of the mixer; feeding the output signal of the mixer into a low pass filter; and measuring the output signal of the low pass filter, with the aid of an output voltage that is normalized to operating voltage of the mixer. A circuit for implementing the method includes a mixer and a low pass filter. The mixer includes a first input for feeding in the first clock signal, and a second input for feeding in the second clock signal. The output of the mixer is connected to the input of the low pass filter.

公开(公告)号：US12039091B2

公开(公告)日：2024-07-16

申请号：US17496055

申请日：2021-10-07

Applicant: Duke University

Inventor： Jonti Talukdar ,  Krishnendu Chakrabarty

IPC: G06F21/75 ,  G11C29/36 ,  H03K19/21

CPC classification number: G06F21/75 ,  G11C29/36 ,  G11C2029/3602 ,  H03K19/21

Abstract: An integrated circuit (IC) protection circuit for an IC includes a controller with a barrier finite state machine (FSM) having a key sequence input that unlocks the controller; and a signal scrambler coupled to receive at least two initialization inputs and a primary input path and output a signal to the IC, wherein at least one initialization input of the at least two initialization inputs is based on an output of the barrier FSM. The IC protection circuit can further include a dynamic authentication circuit coupled to receive the output of the barrier finite state machine and output a signal to the signal scrambler for one of the at least two initialization inputs. The dynamic authentication circuit can be formed of a dynamic sequence generator and a dynamic sequence authenticator, each formed of one or more reconfigurable linear feedback shift registers, and a comparator.