公开(公告)号：US12124593B2

公开(公告)日：2024-10-22

申请号：US17992132

申请日：2022-11-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Wei Ge ,  Chongyang Li ,  Leidong Zheng ,  Yifei Wang

IPC: G06F21/60 ,  G06F8/41 ,  G06F9/445

CPC classification number: G06F21/602

Abstract: The present disclosure discloses an information security application-oriented reconfigurable system chip compiler and an automatic compilation method. The method includes the following steps: firstly, inputting a source program of a cryptographic algorithm; then, executing a software compilation function syntax check of the source program, and when the check result is passed, performing compilation mapping using a compiler; next, executing the cryptographic algorithm by simulation running using a simulator, and generating a configuration code by a simulator array; and finally, guiding a hardware behavior operation using a binary configuration code file generated by the simulator. The reconfigurable system chip compiler includes a source program input module, a software compilation function verification module, a compilation mapping module, a simulation execution module, a configuration code generation module, and a hardware debugging module.

公开(公告)号：US10984313B2

公开(公告)日：2021-04-20

申请号：US16757421

申请日：2019-01-24

Applicant: Southeast University

Inventor： Bo Liu ,  Yu Gong ,  Wei Ge ,  Jun Yang ,  Longxing Shi

IPC: G06N3/063 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544 ,  G06N3/08

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.