公开(公告)号：US20240256018A1

公开(公告)日：2024-08-01

申请号：US18422179

申请日：2024-01-25

Applicant: STMicroelectronics International N.V.

Inventor： Pasquale BUTTA' ,  Alessandro INGLESE ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Riccardo CONDORELLI

IPC: G06F1/24 ,  H03K17/22

CPC classification number: G06F1/24 ,  H03K17/22

Abstract: An electronic device includes at least two electronic components. A reset circuit includes: a parity control circuit; at least two first flip-flops, wherein each first flip-flop has an output coupled to at least one of the at least two electronic components; and at least two second flip-flops, wherein each second flip-flop has at least one output coupled to an input of the parity control circuit.

公开(公告)号：US20240329718A1

公开(公告)日：2024-10-03

申请号：US18606928

申请日：2024-03-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Antonino MONDELLO ,  Alessandro INGLESE ,  Riccardo CONDORELLI

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: A system on chip, SOC circuit comprising a plurality of peripherals configured to be clocked with respective clock signals, wherein the circuit comprises a clock controller configured to produce said respective clock signals via respective clock divide factors, the clock controller comprising a plurality of storage locations having stored therein respective sets of clock divide factors, wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of said respective sets of clock divide factors stored in said plurality of storage locations and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of said respective sets of clock divide factors stored in said plurality of storage locations.