公开(公告)号：US20240256018A1

公开(公告)日：2024-08-01

申请号：US18422179

申请日：2024-01-25

Applicant: STMicroelectronics International N.V.

Inventor： Pasquale BUTTA' ,  Alessandro INGLESE ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Riccardo CONDORELLI

IPC: G06F1/24 ,  H03K17/22

CPC classification number: G06F1/24 ,  H03K17/22

Abstract: An electronic device includes at least two electronic components. A reset circuit includes: a parity control circuit; at least two first flip-flops, wherein each first flip-flop has an output coupled to at least one of the at least two electronic components; and at least two second flip-flops, wherein each second flip-flop has at least one output coupled to an input of the parity control circuit.

公开(公告)号：US20240405798A1

公开(公告)日：2024-12-05

申请号：US18651120

申请日：2024-04-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Salvatore COSTA ,  Michele BOTTARO ,  Pascal FABRE ,  Philippe BOLLARD ,  Felice Alberto TORRISI

IPC: H04B1/7183 ,  H04L7/033

Abstract: Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.

公开(公告)号：US20240242749A1

公开(公告)日：2024-07-18

申请号：US18410049

申请日：2024-01-11

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Michele BOTTARO ,  Salvatore COSTA ,  Jacques TALAYSSAT

IPC: G11C7/24 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/20

Abstract: A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.

公开(公告)号：US20240329718A1

公开(公告)日：2024-10-03

申请号：US18606928

申请日：2024-03-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Antonino MONDELLO ,  Alessandro INGLESE ,  Riccardo CONDORELLI

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: A system on chip, SOC circuit comprising a plurality of peripherals configured to be clocked with respective clock signals, wherein the circuit comprises a clock controller configured to produce said respective clock signals via respective clock divide factors, the clock controller comprising a plurality of storage locations having stored therein respective sets of clock divide factors, wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of said respective sets of clock divide factors stored in said plurality of storage locations and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of said respective sets of clock divide factors stored in said plurality of storage locations.

公开(公告)号：US20240211643A1

公开(公告)日：2024-06-27

申请号：US18541747

申请日：2023-12-15

Applicant: STMicroelectronics International N.V.

Inventor： Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Riccardo CONDORELLI

IPC: G06F21/85 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F21/85 ,  G06F21/602 ,  G06F21/79

Abstract: A SOC includes a core, peripherals, and a bus for interconnecting the core and peripherals. Some peripherals can be selectively enabled or disabled on-demand. The SoC further includes peripheral enabling/disabling electronics and peripheral enabling/disabling circuitry coupled to the peripherals. The peripheral enabling/disabling electronics are directly connected to the peripheral enabling/disabling circuitry and are configured to store information items related to an enabled/disabled peripheral configuration, indicate the peripherals that are enabled and the peripherals that are disabled according to the enabled/disabled peripheral configuration, and provide the peripheral enabling/disabling circuitry with signals based on the stored information items. The peripheral enabling/disabling circuitry allows operation of the enabled peripherals and prevents operation of the disabled peripherals based on the signals received from the peripheral enabling/disabling electronics. The peripheral enabling/disabling electronics implement a secure mechanism allowing access to the peripheral enabling/disabling electronics and modification of the stored information items if security criteria are met.

公开(公告)号：US20240235546A1

公开(公告)日：2024-07-11

申请号：US18409083

申请日：2024-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Daniele MANGANO ,  Fabien LAPLACE ,  Luc GARCIA ,  Michel CUENCA

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/22 ,  G11C5/14

Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.