公开(公告)号：US20140312878A1

公开(公告)日：2014-10-23

申请号：US14322448

申请日：2014-07-02

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Daniele Alfredo BRAMBILLA ,  Fausto REDIGOLO

IPC: H01L21/66 ,  G01R19/00 ,  H01L49/02

CPC classification number: H01L22/20 ,  G01R19/0092 ,  H01L22/12 ,  H01L23/544 ,  H01L28/20 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.

Abstract translation: 对从包括多个堆叠的材料层的材料晶片获得的多个管芯进行索引。 在晶片的相应位置获得每个管芯。 制造阶段包括至少两个步骤，用于使用至少一个光刻掩模通过在时间上连续地暴露于合适的辐射来处理对应于所述多个管芯的子集的材料晶片的相应表面部分。 该方法可以包括通过形成指示材料晶片的表面部分的位置的外部指标来指示相应管芯的位置来指示每个管芯上的管芯指数，该外部指数对应于包括所述管芯的多个管芯的子集 并且可以包括通过相应的公共控制线彼此电耦合的多个电子部件。