公开(公告)号：US20230393198A1

公开(公告)日：2023-12-07

申请号：US18324583

申请日：2023-05-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Diego ALAGNA ,  Alessandro CANNONE

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/08

CPC classification number: G01R31/3177 ,  G06F1/08 ,  G01R31/31725

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

公开(公告)号：US20230064438A1

公开(公告)日：2023-03-02

申请号：US17460657

申请日：2021-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro CANNONE ,  Enrico FERRARA ,  Nicola ERRICO ,  Gea DONZELLI

IPC: H01L21/66 ,  G01R31/28

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.