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公开(公告)号：US20200381072A1
公开(公告)日：2020-12-03
申请号：US16870757
申请日：2020-05-08
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Luca SASSELLI
Abstract: A device includes serial cyclic redundancy check (CRC) processing circuitry and parallel CRC processing circuitry. The serial CRS processing circuitry, in operation, generates a set of intermediate CRC bits based on a first set of seed bits and input data. The parallel CRC processing circuitry is coupled to the serial CRC processing circuitry, and, in operation, generates, using the set of intermediate CRC bits as a set of parallel seed bits and using null input bits, a set of output CRC bits corresponding to the input data.
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