公开(公告)号：US11757686B2

公开(公告)日：2023-09-12

申请号：US17816177

申请日：2022-07-29

Applicant: STMICROELECTRONICS SA

Inventor： Eric Andre ,  Lionel Vogt

IPC: H04B7/06 ,  H04L27/10 ,  H04L27/12 ,  H04L27/16

CPC classification number: H04L27/106 ,  H04L27/12 ,  H04L27/16

Abstract: In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

公开(公告)号：US20230034119A1

公开(公告)日：2023-02-02

申请号：US17816177

申请日：2022-07-29

Applicant: STMICROELECTRONICS SA

Inventor： Eric Andre ,  Lionel Vogt

IPC: H04L27/10 ,  H04L27/12 ,  H04L27/16

Abstract: In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.