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公开(公告)号:US20210305306A1
公开(公告)日:2021-09-30
申请号:US17211739
申请日:2021-03-24
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor: Thierry BERGER , Marc NEYENS , Audrey Vandelle BERTHOUD , Marc GUILLERMET , Philippe BRUN
IPC: H01L27/146
Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.
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公开(公告)号:US20220181390A1
公开(公告)日:2022-06-09
申请号:US17543004
申请日:2021-12-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor: Thierry BERGER , Stephane ALLEGRET-MARET
Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.
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公开(公告)号:US20210305309A1
公开(公告)日:2021-09-30
申请号:US17211723
申请日:2021-03-24
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor: Thierry BERGER , Damien JEANJEAN
IPC: H01L27/146
Abstract: The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.
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