公开(公告)号：US20240235555A9

公开(公告)日：2024-07-11

申请号：US18402958

申请日：2024-01-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/1735

Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

公开(公告)号：US11901894B2

公开(公告)日：2024-02-13

申请号：US17556365

申请日：2021-12-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/1735

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.

公开(公告)号：US12244309B2

公开(公告)日：2025-03-04

申请号：US18402958

申请日：2024-01-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

公开(公告)号：US11211932B1

公开(公告)日：2021-12-28

申请号：US16951645

申请日：2020-11-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

Abstract: A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.

公开(公告)号：US20240137025A1

公开(公告)日：2024-04-25

申请号：US18402958

申请日：2024-01-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/1735

Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

公开(公告)号：US20220116043A1

公开(公告)日：2022-04-14

申请号：US17556365

申请日：2021-12-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Elias El Haddad ,  Tanguy Tromelin ,  Patrick Bougant ,  Christophe Matheron

IPC: H03K19/173

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.