公开(公告)号：US20230134063A1

公开(公告)日：2023-05-04

申请号：US17970351

申请日：2022-10-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Rosalia GERMANA-CARPINETO ,  Lia MASOERO

IPC: H01L29/423 ,  H01L29/78

Abstract: The present description concerns an electronic device comprising a semiconductor substrate, transistors having their gates contained in first trenches extending in the substrate, and at least one electronic component, different from a transistor, at least partly formed in a first semiconductor region contained in a second trench extending in the semiconductor substrate parallel to the first trenches.

公开(公告)号：US20230019484A1

公开(公告)日：2023-01-19

申请号：US17861329

申请日：2022-07-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lia MASOERO ,  Patrick CALENZO

IPC: H01L27/112

Abstract: A one-time programmable memory cell includes a transistor coupled to a capacitor. The transistor includes at least one first conductive gate element arranged in at least one first trench formed in a semiconductor substrate, and at least one first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.

公开(公告)号：US20230121961A1

公开(公告)日：2023-04-20

申请号：US17960064

申请日：2022-10-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Rosalia GERMANA-CARPINETO ,  Lia MASOERO ,  Luigi INNACOLO

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: The present disclosure relates to an electronic device comprising a semiconductor substrate and transistors having their gates contained in trenches extending in the semiconductor substrate, each transistor comprising a doped semiconductor well of a first conductivity type, the well being buried in the semiconductor substrate and in contact with two adjacent trenches among said trenches, a first doped semiconductor region of a second conductivity type, covering the well, in contact with the well, and in contact with the two adjacent trenches, a second doped semiconductor region of the second conductivity type more heavily doped than the first semiconductor region, extending in the first semiconductor region, and a third doped semiconductor region of the first conductivity type, more heavily doped than the well, covering the well, in contact with the first region, and extending in the semiconductor substrate in contact with the well.