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公开(公告)号：US11340798B2
公开(公告)日：2022-05-24
申请号：US16898921
申请日：2020-06-11
Inventor： William Orlando , Julien Couvrand , Pierre Guillemin
Abstract: A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.
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2.发明授权公开(公告)号：US11113384B2
公开(公告)日：2021-09-07
申请号：US15847827
申请日：2017-12-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pierre Guillemin , William Orlando
Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.
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公开(公告)号：US20180181748A1
公开(公告)日：2018-06-28
申请号：US15847827
申请日：2017-12-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pierre Guillemin , William Orlando
IPC: G06F21/52
CPC classification number: G06F21/52 , G06F2221/2123 , G06F2221/2153
Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in at least one internal memory coupled to the processing unit. A plurality of comparators in the hardware monitor circuit are arranged to accept values from the at least one internal memory and gating logic coupled to the plurality of comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the at least one internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.
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