公开(公告)号：US20220066498A1

公开(公告)日：2022-03-03

申请号：US17393492

申请日：2021-08-04

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek Kishore KAUL ,  Jeet Narayan TIWARI

IPC: G06F1/04

Abstract: An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N−1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.