公开(公告)号：US20210281254A1

公开(公告)日：2021-09-09

申请号：US17193532

申请日：2021-03-05

Applicant: STMicroelectronics International N.V.

Inventor： Jeet Narayan TIWARI ,  Anand KUMAR ,  Prashutosh GUPTA

IPC: H03K5/00 ,  H03K19/20

Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

公开(公告)号：US20230068753A1

公开(公告)日：2023-03-02

申请号：US17821398

申请日：2022-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Jeet Narayan TIWARI

IPC: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

公开(公告)号：US20200153442A1

公开(公告)日：2020-05-14

申请号：US16740871

申请日：2020-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Nitin GUPTA ,  Jeet Narayan TIWARI

IPC: H03L7/07 ,  H03L7/095 ,  H03L7/099

Abstract: A method of quickly locking a locked loop includes generating an intermediate reference signal having an intermediate reference frequency between a desired output frequency and a reference frequency of a reference signal, and setting an output frequency of a controllable oscillator to the desired output frequency using a first locked loop having a first loop divider value. The first loop divider value is set such that the intermediate reference frequency multiplied by the first loop divider value is equal to the desired output frequency. The controllable oscillator is then coupled to a second locked loop when the first locked loop locks, with the second locked loop is being activated. The first locked loop is then deactivated.

公开(公告)号：US20240056091A1

公开(公告)日：2024-02-15

申请号：US18363582

申请日：2023-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Jeet Narayan TIWARI

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0626 ,  H03M1/1255 ,  H03M1/1071

Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.

公开(公告)号：US20220066498A1

公开(公告)日：2022-03-03

申请号：US17393492

申请日：2021-08-04

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek Kishore KAUL ,  Jeet Narayan TIWARI

IPC: G06F1/04

Abstract: An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N−1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.