公开(公告)号：US20250132673A1

公开(公告)日：2025-04-24

申请号：US18489410

申请日：2023-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Niccolò Brambilla ,  Valeria Bottarel ,  Sandro Rossi ,  Alessandro Saccà

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08

Abstract: A DC/DC converter including a low side and a high side is disclosed. The converter includes a first switching device being part of the low side, a low side current generator configured to generate a low side current flowing in the first switching device, a second switching device, a compensation resistor coupled in series to the second switching device, a valley current reference current generator configured to generate a valley current threshold current (Ivalclth) flowing in the second switching device and in the compensation resistor for obtaining a first voltage value, and a comparator configured to compare the first voltage value and a reference voltage for generating an error signal as a function of the comparison, the error signal controlling a conductivity of the first switching device of the low side.

公开(公告)号：US20250112542A1

公开(公告)日：2025-04-03

申请号：US18480332

申请日：2023-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Sandro Rossi ,  Alessandro Saccà ,  Niccolò Brambilla ,  Valeria Bottarel

IPC: H02M1/08 ,  H02M3/157 ,  H02M3/158 ,  H03K17/687 ,  H03K19/20

Abstract: According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.