公开(公告)号：US20240312495A1

公开(公告)日：2024-09-19

申请号：US18676354

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US20250029664A1

公开(公告)日：2025-01-23

申请号：US18807793

申请日：2024-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Arpit VIJAYVERGIA ,  Vikas RANA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US20210375333A1

公开(公告)日：2021-12-02

申请号：US17321344

申请日：2021-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C7/06

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US20220208279A1

公开(公告)日：2022-06-30

申请号：US17548096

申请日：2021-12-10

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Arpit VIJAYVERGIA ,  Vikas RANA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US20220165339A1

公开(公告)日：2022-05-26

申请号：US17527031

申请日：2021-11-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C16/30 ,  H02M3/07

Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.