公开(公告)号：US20240312495A1

公开(公告)日：2024-09-19

申请号：US18676354

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US20210281172A1

公开(公告)日：2021-09-09

申请号：US17313533

申请日：2021-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07

Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

公开(公告)号：US20190267380A1

公开(公告)日：2019-08-29

申请号：US15908575

申请日：2018-02-28

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Fabio DE SANTIS ,  Vikas RANA

IPC: H01L27/105 ,  H01L27/11521 ,  G11C29/00 ,  H01L27/112

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20160315611A1

公开(公告)日：2016-10-27

申请号：US14697461

申请日：2015-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Amit CHHABRA

IPC: H03K17/687 ,  H01L23/50 ,  H01L23/34 ,  H01L27/12 ,  H01L27/092

CPC classification number: H03K17/693 ,  H01L27/092 ,  H01L27/1203 ,  H03K17/005 ,  H03K2217/0018

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 体偏置电压发生器产生正的体偏置电压和负体偏置电压的接地体偏置电压。 复用器基于半导体衬底的温度，将正，负或接地体偏置电压中的一个选择性地输出到半导体衬底的掺杂阱区。

公开(公告)号：US20140233321A1

公开(公告)日：2014-08-21

申请号：US14266468

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US20250029664A1

公开(公告)日：2025-01-23

申请号：US18807793

申请日：2024-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Arpit VIJAYVERGIA ,  Vikas RANA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US20230206971A1

公开(公告)日：2023-06-29

申请号：US18175375

申请日：2023-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Vivek TYAGI ,  Vikas RANA ,  Chantal AURICCHIO ,  Laura CAPECCHI

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/222

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20220180944A1

公开(公告)日：2022-06-09

申请号：US17542323

申请日：2021-12-03

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Neha DALAL

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

公开(公告)号：US20220158550A1

公开(公告)日：2022-05-19

申请号：US17494451

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Neha DALAL

IPC: H02M3/07

Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

公开(公告)号：US20160065220A1

公开(公告)日：2016-03-03

申请号：US14474091

申请日：2014-08-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas RANA ,  Ganesh RAJ R

IPC: H03L1/00 ,  H03K3/03

CPC classification number: H03L1/00 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L1/022 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/148 ,  H03L7/18

Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.

Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。