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1.发明公开公开(公告)号：US20230206032A1
公开(公告)日：2023-06-29
申请号：US18172979
申请日：2023-02-22
Inventor： Giuseppe DESOLI , Carmine CAPPETTA , Thomas BOESCH , Surinder Pal SINGH , Saumya SUNEJA
CPC classification number: G06N3/045 , G06F16/2282 , G06N3/04 , G06N3/063 , G06N3/08 , G06F18/217
Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
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公开(公告)号：US20240330660A1
公开(公告)日：2024-10-03
申请号：US18426128
申请日：2024-01-29
Applicant: STMicroelectronics International N.V.
Inventor： Carmine CAPPETTA , Surinder Pal SINGH , Giuseppe DESOLI , Thomas BOESCH , Michele ROSSI
IPC: G06N3/0464 , G06N3/063
CPC classification number: G06N3/0464 , G06N3/063
Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.
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3.发明公开公开(公告)号：US20240330677A1
公开(公告)日：2024-10-03
申请号：US18192589
申请日：2023-03-29
Applicant: STMicroelectronics International N.V.
Inventor： Carmine CAPPETTA , Paolo Sergio ZAMBOTTI , Thomas BOESCH , Giuseppe DESOLI
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.
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公开(公告)号：US20240330399A1
公开(公告)日：2024-10-03
申请号：US18194108
申请日：2023-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Carmine CAPPETTA , Surinder Pal SINGH , Giuseppe DESOLI , Thomas BOESCH
IPC: G06F17/15
CPC classification number: G06F17/15
Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.
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公开(公告)号：US20200310758A1
公开(公告)日：2020-10-01
申请号：US16833353
申请日：2020-03-27
Inventor： Giuseppe DESOLI , Thomas BOESCH , Carmine CAPPETTA , Ugo Maria IANNUZZI
Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.
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Patent Agency Ranking
公开(公告)号：US20230084985A1
公开(公告)日：2023-03-16
申请号：US18056937
申请日：2022-11-18
Inventor： Thomas BOESCH , Giuseppe DESOLI , Surinder Pal SINGH , Carmine CAPPETTA
Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.
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公开(公告)号：US20220101086A1
公开(公告)日：2022-03-31
申请号：US17039653
申请日：2020-09-30
Inventor： Carmine CAPPETTA , Thomas BOESCH , Giuseppe DESOLI
Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.
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公开(公告)号：US20210397933A1
公开(公告)日：2021-12-23
申请号：US16909673
申请日：2020-06-23
Inventor： Thomas BOESCH , Giuseppe DESOLI , Surinder Pal SINGH , Carmine CAPPETTA
Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.
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公开(公告)号：US20210256346A1
公开(公告)日：2021-08-19
申请号：US16794062
申请日：2020-02-18
Inventor： Giuseppe DESOLI , Carmine CAPPETTA , Thomas BOESCH , Surinder Pal SINGH , Saumya SUNEJA
Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
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公开(公告)号：US20200310761A1
公开(公告)日：2020-10-01
申请号：US16833340
申请日：2020-03-27
Inventor： Michele ROSSI , Giuseppe DESOLI , Thomas BOESCH , Carmine CAPPETTA
Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
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