公开(公告)号：US20140035644A1

公开(公告)日：2014-02-06

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Chittoor PARTHASARATHY ,  Nitin CHAWLA ,  Kallol CHATTERJEE ,  Pascal URARD

IPC: H03K3/02

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20240411519A1

公开(公告)日：2024-12-12

申请号：US18736783

申请日：2024-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Pascal URARD ,  Nathan BAIN

IPC: G06F7/544 ,  G06F5/01 ,  G06F7/50 ,  G06F7/523

Abstract: The present description concerns a circuit configured to perform a multiply and accumulate operation in a layer of an artificial neural network, the operation taking, as an input, an input data value and a weight, and wherein the weight only has a value within a limited set only formed of value 0, of a plurality of values equal to 2n, where n is an integer, and of a plurality of values, each equal to the product of 2n by an odd number greater than or equal to 3.

公开(公告)号：US20190018062A1

公开(公告)日：2019-01-17

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal URARD ,  Florian CACHO ,  Vincent HUARD ,  Alok Kumar TRIPATHI

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181

CPC classification number: G01R31/318342 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/31816 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.