公开(公告)号：US20040104750A1

公开(公告)日：2004-06-03

申请号：US10639248

申请日：2003-08-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajesh Bajaj ,  Nipun Padha

IPC: H03L007/06

CPC classification number: H03L7/18 ,  G06F1/10

Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree.

Abstract translation: 用于数字集成电路的改进的锁相环（PLL）。 该PLL的一个特点是通过时钟树副本将压控振荡器（VCO）输出馈送到相位和频率检测器（PFD）输入，提供等于路由时钟树的延迟。