公开(公告)号：US20150301540A1

公开(公告)日：2015-10-22

申请号：US14788682

申请日：2015-06-30

Applicant: STMicroelectronics Pvt Ltd

Inventor： Hemant Shukla ,  Saurabh Kumar Singh ,  Nitin Bansal

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G05F1/56

Abstract: An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.

Abstract translation: FDSOI集成电路管芯在输出节点上提供基于参考电压的稳压输出电压。 将第一电流传递到输出节点的传输晶体管。 反馈回路基于第一电流产生第二电流并基于第二电流向控制晶体管施加控制信号来调节输出电压。 环路电流适配器通过调整施加到反馈回路的环形晶体管的背栅的背栅偏置电压来适配第一和第二电流的比率。

公开(公告)号：US09025355B2

公开(公告)日：2015-05-05

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics PVT Ltd

Inventor： Fabio De Santis ,  Marco Pasotti ,  Abhishek Lal

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。

公开(公告)号：US20140340133A1

公开(公告)日：2014-11-20

申请号：US14276567

申请日：2014-05-13

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics Pvt. Ltd.

Inventor： Gilles Gasiot ,  Sylvain Clerc ,  Junaid Yousuf ,  Maximilien Glorieux

IPC: H03K19/003 ,  H03L7/08

CPC classification number: H03K19/0033 ,  G11C5/005 ,  H03K3/0375 ,  H03K3/356121 ,  H03L7/08 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/095 ,  H03L7/18

Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

Abstract translation: 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。

公开(公告)号：US20130271107A1

公开(公告)日：2013-10-17

申请号：US13722594

申请日：2012-12-20

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Pvt. Ltd.

Inventor： Nicolas Bernard Grossier ,  Sabyasachi Das ,  V Srinivasan

IPC: G05F1/56

CPC classification number: G05F1/56 ,  G01R31/00 ,  G01R31/31924 ,  G05F1/10

Abstract: A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage. The Voltage regulator is configured, during a start-up phase of a test operation mode, to receive a control signal equal to the input supply voltage, is configured to receive the input supply voltage having a substantially increasing trend, detect that the input supply voltage is equal to a first voltage threshold and generate, as a function of the detected signal and of the control signal, a by-pass signal having a transition from a first logic value to a second logic value for indicating a by-pass status of the Voltage regulator, and is configured to receive the by-pass signal having the second logic value and open the power transistor. The second input terminal is configured, during the test operation mode, to receive the test supply voltage having a test value different from a nominal value of the regulated output supply voltage.

Abstract translation: 电压调节器包括被配置为接收输入电源电压的第一输入端子，包括被配置为接收作为输入电源电压的函数的调节输出电源电压或者接收测试电源电压的第二输入端子，并且包括功率晶体管，包括 输入端子，被配置为接收所述输入电源电压并且包括被配置为产生所述稳定的输出电源电压的输出端子。 电压调节器在测试操作模式的启动阶段被配置为接收等于输入电源电压的控制信号，被配置为接收具有基本上增加的趋势的输入电源电压，检测输入电源电压 等于第一电压阈值，并且根据所检测的信号和控制信号产生具有从第一逻辑值到第二逻辑值的转变的旁路信号，用于指示所述第一电压阈值的旁路状态 电压调节器，并且被配置为接收具有第二逻辑值的旁路信号并且打开功率晶体管。 在测试操作模式期间，第二输入端被配置为接收具有与调节输出电源电压的标称值不同的测试值的测试电源电压。

公开(公告)号：US20130181754A1

公开(公告)日：2013-07-18

申请号：US13784571

申请日：2013-03-04

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Nitin GUPTA

IPC: H03L7/199

CPC classification number: H03L7/199 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/091 ,  H04L7/0337

Abstract: In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.

Abstract translation: 在从接收到的数字数据流中恢复基座的方法以及从接收的数字数据流中恢复时钟的装置中，从接收器的基座产生相移的停靠信号。 在选择一个相移时钟信号之后，确定另外两个相移时钟信号。 根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值，增加和比较计数器值。 如果需要，相移时钟信号的选择和对输入数字数据流进行采样的步骤，比较值和增加计数器值，直到计数器值的比较结果指示后一个确定的相位时钟信号之一， 移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。

公开(公告)号：US20130170081A1

公开(公告)日：2013-07-04

申请号：US13626131

申请日：2012-09-25

Applicant: STMICROELECTRONICS PVT LTD

Inventor： Gaurav Singh

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.

Abstract translation: 电路包括被配置为放电静电电荷的放电装置。 放电装置具有放电状态。 第一电路被配置为当感测静电电荷时向放电装置提供脉冲。 脉冲使排出装置进入排出状态。 第二电路被配置为在脉冲结束之后将放电配置保持在放电状态。 第三电路被配置为接收脉冲并向放电装置提供延迟的输出。 延迟输出导致放电装置退出放电状态。

公开(公告)号：US20040153923A1

公开(公告)日：2004-08-05

申请号：US10667199

申请日：2003-09-18

Applicant: STMicroelectronics Pvt, Ltd.

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G01R031/28

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value nullnnull. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。

公开(公告)号：US20040136253A1

公开(公告)日：2004-07-15

申请号：US10679941

申请日：2003-10-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Anuj Gupta ,  Sanjeev Chopra

IPC: G11C007/00

CPC classification number: G11C7/065

Abstract: An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.

Abstract translation: 具有形成锁存器的两个交叉耦合的反相器的改进的锁存型读出放大器电路，用于选择性地将锁存器连接到电源的电源耦合装置和用于选择性地将每个反相器的输入连接到补充位的位线耦合电路 线从内存阵列。 该电路被配置为通过提供延迟读出放大器使能信号来传递晶体管来延迟位线从读出放大器的断开直到闭锁动作完成，并且将两个晶体管加到 与常规锁存器的现有晶体管串联，用于校正锁存器的反相器的阈值电压之间的偏移。

公开(公告)号：US20040108875A1

公开(公告)日：2004-06-10

申请号：US10662952

申请日：2003-09-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajesh Kaushik ,  Rajesh Narwal

IPC: H03B001/00

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。

公开(公告)号：US20040061524A1

公开(公告)日：2004-04-01

申请号：US10611322

申请日：2003-07-01

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Sunil Chandra Kasanyal

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Abstract translation: 用于数字逻辑电路的电压电平转换器具有相同的上升和下降延迟的高电平到低电平电压转换。 电压电平转换器可以包括输入高压逻辑逆变器（以高电压电平工作），并通过电压降低电路连接到在低电压电平下工作的输出低压逻辑逆变器。 用于提供高电平到低电压平移的相关方法可以包括提供在高电压电平下工作的输入逆变器和在低电压电平下工作的输出逆变器。 此外，在将高压逆变器的输出电压降低到所需水平之后，高压逆变器的输出可以耦合到低压逆变器的输入。