公开(公告)号：US20020079589A1

公开(公告)日：2002-06-27

申请号：US10046322

申请日：2001-10-23

Applicant: STMicroelectronics S.A.

Inventor： Philippe Gayet ,  Eric Granger

IPC: H01L021/4763 ,  H01L023/02

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. Further, at least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer.

Abstract translation: 一种用于制造集成电路的方法。 根据该方法，在第一电介质层的上方形成第二电介质层，并且在第一和第二电介质层中蚀刻空穴和/或沟槽。 孔和/或沟槽用金属填充以形成电连接元件，并且形成至少第三介电层。 为了控制蚀刻的深度，孔和/或沟槽相对于第一介电层和元件在第三介电层和第二介质层中被选择性蚀刻。 此外，提供了一种具有由电介质层分离的金属化水平和连接不同金属化水平线的金属化通孔的类型的集成电路。 集成电路包括第一和第二金属化层，位于第一金属化层上方的第一和第二叠置电介质层，以及位于第一和第二电介质层上方的第三电介质层。 此外，至少一个电连接元件设置在第三电介质层中并且通过第二电介质层，直到其与第一电介质层接触。