公开(公告)号：US20020143837A1

公开(公告)日：2002-10-03

申请号：US10035033

申请日：2001-12-28

Applicant: STMicroelectronics S.A.

Inventor： Olivier Duborgel

IPC: G06F007/38

CPC classification number: G06F7/5095 ,  G06F7/5443

Abstract: The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to Nnull1 bits. A circuit for determining the output carry value associated with the result is also provided.

Abstract translation: 算术单元的微架构包括两个级联的N位加法器，以在累加器中提供N位结果。 算术单元还包括进位保存加法器，后跟一个加法器，它与累加器一起扩展到N + 1位。 还提供了用于确定与结果相关联的输出进位值的电路。