公开(公告)号：US20040210730A1

公开(公告)日：2004-10-21

申请号：US10700361

申请日：2003-11-03

Applicant: STMicroelectronics S.A.

Inventor： Pierre Marty ,  Rey Gaelle ,  Pascal Chauvet

IPC: G06F012/00

CPC classification number: G11C7/22 ,  G06F13/1673

Abstract: A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.

Abstract translation: 一种用于控制存储器的电路，所述存储器包括不能同时访问的至少两个区域，所述电路包括用于为每个区域分别存储一系列读取和/或写入指令的第一电路，以及用于检测第一 用于第一区域的指令是第一区域不能接收其他指令的周期之后的预定指令，以及在该周期期间向另一个存储区域提供指令的第三电路。