公开(公告)号：US20020170743A1

公开(公告)日：2002-11-21

申请号：US10117463

申请日：2002-04-05

Applicant: STMicroelectronics S.A.

Inventor： Samuel Boret

IPC: H05K001/00

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductance device in monolithic structure is formed from a first metallization level layer of lower parallel conductive lines extending along the inductance pattern; next, on a second level, a set of vias is formed over each underlying conductive line being associated with at least two vias; and in a third metallization level, upper conductive lines interconnected to the underlying conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.

Abstract translation: 单片结构的电感器件由沿电感图形延伸的下并行导线的第一金属化层形成; 接下来，在第二级上，在与至少两个通孔相关联的每个下面的导电线上形成一组通孔; 并且在第三金属化水平中，通过通孔互连到下面的导电线的上导电线，下导电线和上导电线相对于彼此移位以确保电连续性。