公开(公告)号：US20020163364A1

公开(公告)日：2002-11-07

申请号：US10113859

申请日：2002-04-01

Applicant: STMicroelectronics S.A.

Inventor： Sylvain Majcherczak ,  Guy Mabboux

IPC: H03K005/153

CPC classification number: H03K17/302 ,  H03K17/223 ,  H03K19/0016 ,  H03K19/007

Abstract: In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.

Abstract translation: 在集成电路中，检测装置检测集成电路的磁芯的电源电压的下降或相对于集成电路的输入/输出接口电路的电源电压过度缓慢的累积。 通过检测装置将接口电路的输出设置为高阻抗状态，以最小化其功耗。