公开(公告)号：US20030181011A1

公开(公告)日：2003-09-25

申请号：US10351281

申请日：2003-01-24

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Curro ,  Barbara Fazio

IPC: H01L021/336

CPC classification number: H01L29/7813 ,  H01L29/4933

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and the implanted dopants are diffused in the body region.

Abstract translation: 形成沟槽栅极功率MOS晶体管的工艺包括在半导体衬底上形成具有第一导电类型的外延层，并在外延层上形成具有第二导电类型的体区。 在体区域和外延层中形成栅极沟槽。 该工艺还包括锪孔栅极沟槽的上部，以及在包括其上部的栅极沟槽的表面上形成栅极电介质层。 栅极导电层形成在用于限定栅电极的栅极电介质层的表面上。 栅极导电层的厚度不足以完全填充栅极沟槽，从而残留在其中的空腔。 残留的空腔填充有填料层。 在使用填充层作为自对准掩模的同时，从体区的上表面除去栅极导电层。 栅极导电层的边缘表面被氧化。 源区域通过在使用氧化边缘表面作为自对准掩模的同时在体区中注入掺杂剂而形成，并且注入的掺杂剂在体区中扩散。