公开(公告)号：US12132092B2

公开(公告)日：2024-10-29

申请号：US17743992

申请日：2022-05-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/76804 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/4933 ,  H01L29/6656

摘要： Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US12040375B2

公开(公告)日：2024-07-16

申请号：US17249918

申请日：2021-03-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Liang Cheng

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4933 ,  H01L21/3065 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.

公开(公告)号：US12020937B2

公开(公告)日：2024-06-25

申请号：US17701759

申请日：2022-03-23

申请人： GlobalFoundries U.S. Inc.

发明人： Jianwei Peng ,  Hong Yu ,  Man Gu ,  Eric S. Kozarsky

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/45 ,  H01L29/4933

摘要： Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

公开(公告)号：US20240206183A1

公开(公告)日：2024-06-20

申请号：US18591313

申请日：2024-02-29

申请人： Cypress Semiconductor Corporation

发明人： Chun CHEN ,  James PAK ,  Unsoon KIM ,  Inkuk KANG ,  Sung-Taeg KANG ,  Kuo Tung CHANG

IPC分类号： H10B43/40 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35

CPC分类号： H10B43/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35 ,  H01L29/517

摘要： A semiconductor device and methods of fabrication the same are disclosed. In one embodiment, the semiconductor device may include a non-volatile memory (NVM) cell including a memory gate stack and a select gate stack separated by an inter-gate dielectric disposed in a memory region of a substrate, a low voltage field-effect transistor (LVFET) including a first high-K metal-gate (HKMG) stack disposed in a peripheral region of the substrate, and a high voltage field-effect transistor (HVFET) including a second HKMG stack disposed in the peripheral region, in which top surfaces of the memory gate stack and the select gate stack of the NVM cell, the LVFET, and the HVFET have an approximately same elevation from the substrate or are substantially co-planar. Other embodiments are also disclosed within.

公开(公告)号：US20240194535A1

公开(公告)日：2024-06-13

申请号：US18080017

申请日：2022-12-13

申请人： GlobalFoundries U.S. Inc.

发明人： Venkatesh P. Gopinath ,  Navneet Jain ,  Hongru Ren ,  Alexander Derrickson ,  Jianwei Peng ,  Bipul C. Paul

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H10B63/00

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L29/42316 ,  H01L29/4933 ,  H10B63/34

摘要： Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

公开(公告)号：US20240186412A1

公开(公告)日：2024-06-06

申请号：US18441118

申请日：2024-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665

摘要： A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

公开(公告)号：US20240178279A1

公开(公告)日：2024-05-30

申请号：US18307620

申请日：2023-04-26

申请人： SK hynix Inc.

发明人： Wan Sup SHIN ,  Yoon Ho KANG ,  Ji Seong KIM

IPC分类号： H01L29/10 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/68

CPC分类号： H01L29/1033 ,  H01L21/02362 ,  H01L21/823412 ,  H01L29/4933 ,  H01L29/685

摘要： A semiconductor device includes a gate structure including insulating layers and conductive layers that are alternately stacked, a channel layer located in the gate structure, a silicide layer located in the channel layer, and a memory layer surrounding the channel layer. At least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.

公开(公告)号：US11950413B2

公开(公告)日：2024-04-02

申请号：US18079971

申请日：2022-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H10B41/40

CPC分类号： H10B41/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/3212 ,  H01L21/32139 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575

摘要： An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.

公开(公告)号：US11916060B2

公开(公告)日：2024-02-27

申请号：US17845159

申请日：2022-06-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Fu Hsu ,  Ta-Yuan Kung ,  Chen-Liang Chu ,  Chih-Chung Tsai

IPC分类号： H01L21/00 ,  H01L27/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L27/0251 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/0649 ,  H01L29/4933 ,  H01L29/66659

摘要： Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

公开(公告)号：US11908900B2

公开(公告)日：2024-02-20

申请号：US17869885

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yin-Kai Liao ,  Sin-Yi Jiang ,  Hsiang-Lin Chen ,  Yi-Shin Chu ,  Po-Chun Liu ,  Kuan-Chieh Huang ,  Jyh-Ming Hung ,  Jen-Cheng Liu

IPC分类号： H01L29/10 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/1087 ,  H01L29/167 ,  H01L29/4933 ,  H01L29/6659

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.