公开(公告)号：US20030235097A1

公开(公告)日：2003-12-25

申请号：US10449761

申请日：2003-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC: G11C007/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Abstract translation: 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。