公开(公告)号：US20210187663A1

公开(公告)日：2021-06-24

申请号：US17121184

申请日：2020-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio BELLIZZI ,  Michele DERAI

IPC: B23K26/38 ,  H01L21/304

Abstract: A semiconductor substrate such as a semiconductor wafer includes a cutting line having a length. The semiconductor substrate is cut along the line by first selectively applying laser beam ablation energy to the semiconductor substrate a certain locations along the cutting line and then blade sawing along cutting line. The semiconductor substrate thus includes one or more ablated regions as well as one or more unablated regions at the cutting line.

公开(公告)号：US20220384209A1

公开(公告)日：2022-12-01

申请号：US17824703

申请日：2022-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto TIZIANI ,  Antonio BELLIZZI

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56

Abstract: Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.

公开(公告)号：US20230066285A1

公开(公告)日：2023-03-02

申请号：US17895783

申请日：2022-08-25

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Antonio BELLIZZI ,  Guendalina CATALANO

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/495 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56

Abstract: A semiconductor device comprises: one or more semiconductor dice arranged on a substrate such as a leadframe, an insulating encapsulation of, e.g., LDS material molded onto the semiconductor die or dice arranged on the substrate, the encapsulation having a surface opposite the substrate, and electrically conductive formations (e.g., die-to-lead 181, 182, 183 or die-to-die 201, 202) provided in the encapsulation and coupled to the semiconductor die or dice arranged on the substrate. A tape is laminated onto the surface of the encapsulation opposite the substrate and electrically conductive contacts to the electrically conductive formations extend through the tape laminated onto the encapsulation. The length of the electrically conductive contacts is thus reduced to the thickness of the tape laminated onto the encapsulation, thus facilitating producing, e.g., “vertical” MOSFET power devices having a reduced drain-source “on” resistance, RDSON.

公开(公告)号：US20220392863A1

公开(公告)日：2022-12-08

申请号：US17833233

申请日：2022-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio BELLIZZI ,  Marco ROVITTO

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor chip is arranged on a region of laser direct structuring (LDS) material of a laminar substrate. The semiconductor chip has a front active area facing towards, and a metallized back surface facing away from, the laminar substrate. An encapsulation of LDS material on the laminar substrate encapsulates the semiconductor chip with the metallized back surface of the semiconductor chip exposed at an outer surface of the encapsulation of LDS material. Electrically conductive lines and first vias are structured in the region of LDS material to electrically connect to the front active area of the semiconductor chip. A thermally conductive layer is plated over the outer surface of the encapsulation of LDS material in contact with the metallized back surface of the semiconductor chip. A heat extractor body of thermally conductive material is coupled in heat transfer relationship with the thermally conductive layer.

公开(公告)号：US20220352047A1

公开(公告)日：2022-11-03

申请号：US17728298

申请日：2022-04-25

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio BELLIZZI ,  Antonio CANNAVACCIUOLO

IPC: H01L23/31 ,  H01L21/56

Abstract: A semiconductor device, such as a QFN (Quad-Flat No-lead) package, includes an insulating encapsulation of a semiconductor chip. The insulating encapsulation is formed by a first encapsulation material which encapsulates the semiconductor chip and a second encapsulation material that is molded onto an upper surface of the first encapsulation material. The first encapsulation material includes an oblique cavity extending from the upper surface. The second encapsulation material includes an anchoring protrusion that enters into the cavity.