公开(公告)号：US20010049166A1

公开(公告)日：2001-12-06

申请号：US09817799

申请日：2001-03-26

Applicant: STMicroelectronics S.r.l.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/8238

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Abstract translation: 一种用于制造具有存储器件和逻辑电路的集成电路的方法，包括在半导体衬底的第一部分中形成多个第一晶体管，在半导体衬底的第二部分中形成多个第二晶体管，以及多个存储器 在半导体衬底的第三部分中的单元。 用于从半导体衬底的第一和第三部分选择性地去除电介质层的矩阵掩模允许电介质保留在多个存储单元的浮置栅极和多个第一晶体管的栅电极上。 然后在浮动栅极上形成控制栅极，该栅极由电介质分离。 多个第一晶体管的栅电极的一部分保持自由，以便与晶体管接触。

公开(公告)号：US20010018250A1

公开(公告)日：2001-08-30

申请号：US09727266

申请日：2000-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Barbara Crivelli ,  Daniela Peschiaroli ,  Elisabetta Palumbo ,  Nicola Zatelli

IPC: H01L021/8234

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.